d-Matrix and AIchip have completed validation of a jointly developed 3D-stacked DRAM technology, paving the way for its use in d-Matrix’s upcoming Raptor inference accelerators. The companies say the memory architecture may offer up to a tenfold increase in inference speeds compared with current HBM4-based accelerators.
The 3D DRAM, developed in collaboration between US-based d-Matrix and Taiwan’s AIchip, is positioned as an alternative to existing high-bandwidth memory solutions widely used in AI hardware. The new design, described as 3DIMC (3D stacked digital in-memory compute), is currently undergoing testing on d-Matrix’s Pavehawk chips.
d-Matrix, which entered the data-centre inference market when supply constraints affected availability of Nvidia hardware, plans to introduce the technology in its forthcoming Raptor accelerator series. The Raptor models are intended to replace the company’s Corsair line of compute cards, its first dedicated hardware offering.
According to preliminary estimates shared by the company, the 3DIMC memory could deliver up to ten times higher inference performance than existing accelerators based on HBM4. The companies also state that the design aims to address performance and cost limitations associated with current AI infrastructure.
Company representatives have indicated that the development aligns with a longer-term effort to design architectures suited to growing demand for generative and agent-based AI workloads.
d-Matrix’s initial compute card, the Corsair C8, marked the company’s entry into data-centre inference hardware. The forthcoming Raptor accelerators will be the first commercial products to incorporate the 3D-stacked DRAM technology. Further technical specifications and availability details are expected to be outlined closer to commercial release. |
